1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit for providing plural scan signals and plural emission signals.
2. Description of the Prior Art
Along with the advantages of thin appearance, low power consumption, and low radiation, flat panel displays have been widely applied in various electronic products such as computer monitors, mobile phones, personal digital assistants (PDAs), or flat panel televisions. In general, the flat panel display comprises plural pixel units, a shift register circuit, and a source driver. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit is employed to generate plural scan signals furnished to the pixel units for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art shift register circuit 100. As shown in FIG. 1, the shift register circuit 100 comprises a plurality of shift register stages and, for ease of explanation, illustrates an (N−1)th shift register stage 111, an Nth shift register stage 112 and an (N+1)th shift register stage 113. Each shift register stage is utilized for generating one corresponding scan signal furnished to one corresponding scan line according to a first clock CK1 and a second clock CK2 having a phase opposite to the first clock CK1. For instance, the Nth shift register stage 112 includes a plurality of P-type thin film transistors for generating a scan signal SSn furnished to a scan line LSn based on the first clock CK1, the second clock CK2, a low reference voltage Vgl and a high reference voltage Vgh.
FIG. 2 is a schematic diagram showing related signal waveforms regarding the operation of the shift register circuit 100 shown in FIG. 1, having time along the abscissa. The signal waveforms in FIG. 2, from top to bottom, are the first clock CK1, the second clock CK2, the scan signal SSn−1, the scan signal SSn and the scan signal SSn+1. As shown in FIG. 2, the pulse widths of the scan signals SSn−1˜SSn+1 generated by the shift register circuit 100 are substantially identical to the pulse width of the first clock CK1. With the aim of enhancing image quality of flat panel displays, extra threshold compensation mechanism is commonly added to each pixel unit for providing an accurate control of pixel brightness. However, in order to properly operate the pixel unit with threshold compensation mechanism for enhancing image quality, emission signals are further required to assist the scan signals in performing related driving operations and, moreover, the pulse widths of the emission signals or the scan signals are required to be greater than the pulse width of the first clock CK1, e.g. twice the pulse width of the first clock CK1. In view of that, the prior-art shift register circuit 100 is not suitable for use in driving the pixel units with threshold compensation mechanism.